View IS42S32200E-6TL_4581835.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IS42S32200E IS45S32200E
512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
FEATURES
* Clockfrequency:200,166,143,133MHz * Fullysynchronous;allsignalsreferencedtoa positive clock edge * Internalbankforhidingrowaccess/precharge * Single3.3Vpowersupply * LVTTLinterface * Programmableburstlength: (1,2,4,8,fullpage) * Programmableburstsequence: Sequential/Interleave * Selfrefreshmodes * 4096refreshcyclesevery16ms(A2grade)or 64ms(Commercia,Industrial,A1grade) * Randomcolumnaddresseveryclockcycle * ProgrammableCASlatency(2,3clocks) * Burstread/writeandburstread/singlewrite operations capability * Burstterminationbyburststopandprecharge command AUGUST 2009
organizedas524,288bitsx32-bitx4-bankforimproved performance. The synchronous DRAMs achieve highspeed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
OVERVIEW ISSI's 64Mb Synchronous DRAM IS42/45S32200E is
KEY TIMING PARAMETERS
Parameter ClkCycleTime CASLatency=3 CASLatency=2 ClkFrequency CASLatency=3 CASLatency=2 AccessTimefromClock CASLatency=3 CASLatency=2 -5 -6 5 6 10 10 200 166 100 100 5 5.5 8 8 -7 -75E 7 - 10 7.5 143 - 100 133 5.5 - 8 5.5 Unit ns ns Mhz Mhz ns ns
OPTIONS
* Packages: 86-pinTSOP-II 90-ballTF-BGA * Operatingtemperaturerange: Commercial (0oC to + 70oC) Industrial(-40oCto+85oC) AutomotiveGrade,A1(-40oCto+85oC) AutomotiveGrade,A2:(-40oCto+105oC)
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
1
IS42S32200E, IS45S32200E
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memorysystemscontaining67,108,864bits.Internally configured as a quad-bank DRAM with a synchronous interface.Each16,777,216-bitbankisorganizedas2,048 rowsby256columnsby32bits. The64MbSDRAMincludesanAUTOREFRESHMODE, and a power-saving, power-down mode. All signals are registeredonthepositiveedgeoftheclocksignal,CLK. AllinputsandoutputsareLVTTLcompatible. The64MbSDRAMhastheabilitytosynchronouslyburst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequenceisavailablewiththeAUTOPRECHARGEfunction enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followedbyaREADorWRITEcommand.TheACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1selectthebank;A0-A10selecttherow).TheREAD or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. ProgrammableREADorWRITEburstlengthsconsistof 1,2,4and8locationsorfullpage,withaburstterminate option.
FUNCTIONAL BLOCK DIAGRAM
CLK CKE CS RAS CAS WE
DQM0-3 COMMAND DECODER & CLOCK GENERATOR
DATA IN BUFFER
32 32
MODE REGISTER
11
REFRESH CONTROLLER
DQ 0-31
SELF REFRESH CONTROLLER
A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1
11
32
DATA OUT BUFFER
VDD/VDDQ GND/GNDQ
32
REFRESH COUNTER
2048 2048 2048 2048
ROW DECODER
MULTIPLEXER
11
MEMORY CELL ARRAY
ROW ADDRESS LATCH
11
ROW ADDRESS BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN ADDRESS LATCH
256 (x 32)
BANK CONTROL LOGIC
BURST COUNTER COLUMN ADDRESS BUFFER
COLUMN DECODER
2
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE CAS RAS CS NC BA0 BA1 A10 A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
PIN DESCRIPTIONS
A0-A10 A0-A7 BA0,BA1 DQ0toDQ31 CLK CKE CS RAS CAS RowAddressInput Column Address Input BankSelectAddress DataI/O SystemClockInput ClockEnable Chip Select RowAddressStrobeCommand Column Address Strobe Command WE DQM0-DQM3 Vdd Vss Vddq Vssq NC WriteEnable x32Input/OutputMask Power Ground PowerSupplyforI/OPin GroundforI/OPin No Connection
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
3
IS42S32200E, IS45S32200E
PIN CONFIGURATION PACKAGECODE:B90BALLTF-BGA(TopView)(8.00mmx13.00mmBody,0.8mmBallPitch)
123456789 A B C D E F G H J K L M N P R
PIN DESCRIPTIONS
A0-A10 A0-A7 BA0,BA1 DQ0toDQ31 CLK CKE CS RAS CAS RowAddressInput Column Address Input BankSelectAddress DataI/O SystemClockInput ClockEnable Chip Select RowAddressStrobeCommand Column Address Strobe Command WE DQM0-DQM3 Vdd Vss Vddq Vssq NC WriteEnable x32Input/OutputMask Power Ground PowerSupplyforI/OPin GroundforI/OPin No Connection
DQ26 DQ24
VSS
VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC A2 A10 NC BA0 CAS VDD DQ6 DQ1 DQ16 VSSQ DQM2 VDD A0 BA1 CS A1 NC RAS
DQ28 VDDQ VSSQ VSSQ DQ27 DQ25 VSSQ DQ29 DQ30 VDDQ DQ31 VSS DQM3 A4 A7 CLK DQM1 A5 A8 CKE NC NC A3 A6 NC A9 NC VSS
WE DQM0 DQ7 VSSQ DQ5 VDDQ DQ3 VDDQ
VDDQ DQ8
VSSQ DQ10 DQ9 VSSQ DQ12 DQ14 DQ11 VDDQ VSSQ DQ13 DQ15 VSS
VDDQ VSSQ DQ4 VDD DQ0 DQ2
4
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
PIN FUNCTIONS
Symbol A0-A10 Pin No. (TSOP) 25to27 60 to 66 24 Type InputPin Function (In Detail) AddressInputs:A0-A10aresampledduringtheACTIVE command(row-addressA0-A10)andREAD/WRITEcommand(A0-A7 withA10definingautoprecharge)toselectonelocationoutofthememoryarray intherespectivebank.A10issampledduringaPRECHARGEcommandtodetermineifallbanksaretobeprecharged(A10HIGH)orbankselectedby BA0,BA1(LOW).Theaddressinputsalsoprovidetheop-codeduringaLOAD MODEREGISTERcommand. BankSelectAddress:BA0andBA1defineswhichbanktheACTIVE,READ,WRITE orPRECHARGEcommandisbeingapplied. CAS, in conjunction with the RAS and WE, forms the device command. See the "CommandTruthTable"fordetailsondevicecommands. TheCKEinputdetermineswhethertheCLKinputisenabled.Thenextrisingedge oftheCLKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW.WhenCKE isLOW,thedevicewillbeineitherpower-downmode,clocksuspendmode,orself refresh mode. CKEisan asynchronous input. CLKisthemasterclockinputforthisdevice.ExceptforCKE,allinputstothisdevice areacquiredinsynchronizationwiththerisingedgeofthispin. TheCS input determines whether command input is enabled within the device. Command input is enabled when CSisLOW,anddisabledwithCSisHIGH.The device remains in the previous state when CSisHIGH. DQ0toDQ15areDQpins.DQthroughthesepinscanbecontrolledinbyteunits usingtheDQM0-DQM3pins
BA0,BA1 CAS CKE
22,23 18 67
InputPin InputPin InputPin
CLK CS
68 20
InputPin InputPin
DQ0to 2,4,5,7,8,10,11,13 DQ31 74,76,77,79,80,82,83,85 45,47,48,50,51,53,54,56 31,33,34,36,37,39,40,42 DQM0 16,28,59,71 DQM3
DQPin
InputPin
RAS WE Vddq Vdd GNdq GNd
19 17 3,9,35,41,49,55,75,81 1,15,29,43 6,12,32,38,46,52,78,84 44,58,72,86
InputPin InputPin SupplyPin SupplyPin SupplyPin SupplyPin
DQMxcontrolthelowerandupperbytesoftheDQbuffers.Inreadmode, theoutputbuffersareplaceinaHigh-Zstate.DuringaWRITEcycletheinputdata ismasked.WhenDQMxissampledHIGHandisaninputmasksignalforwrite accessesandanoutputenablesignalforreadaccesses.DQ0throughDQ7are controlledbyDQM0.DQ8throughDQ15arecontrolledbyDQM1.DQ16through DQ23arecontrolledbyDQM2.DQ24throughDQ31arecontrolledbyDQM3. RAS, in conjunction with CAS and WE, forms the device command. See the "CommandTruthTable"itemfordetailsondevicecommands. WE, in conjunction with RAS and CAS, forms the device command. See the "CommandTruthTable"itemfordetailsondevicecommands. Vddq is the output buffer power supply. Vdd is the device internal power supply. GNdq is the output buffer ground. GNd is the device internal ground.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
5
IS42S32200E, IS45S32200E
READ
TheREADcommandselectsthebankfromBA0,BA1inputs and starts a burst read access to an active row. Inputs A0-A7providesthestartingcolumnlocation.WhenA10is HIGH,thiscommandfunctionsasanAUTOPRECHARGE command.Whentheautoprechargeisselected,therow beingaccessedwillbeprechargedattheendoftheREAD burst.Therowwillremainopenforsubsequentaccesses when AUTO PRECHARGE is not selected. DQ's read dataissubjecttothelogiclevelontheDQMinputstwo clocksearlier.WhenagivenDQMsignalwasregistered HIGH,thecorrespondingDQ'swillbeHigh-Ztwoclocks later.DQ'swillprovidevaliddatawhentheDQMsignal wasregisteredLOW. AUTOPRECHARGEdoesnotapplyexceptinfull-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed.
AUTO REFRESH COMMAND
ThiscommandexecutestheAUTOREFRESHoperation. Therowaddressandbanktoberefreshedareautomatically generatedduringthisoperation. Thestipulatedperiod(trc)is requiredforasinglerefreshoperation,andnoothercommandscanbeexecutedduringthisperiod. Thiscommand isexecutedatleast4096timeseverytref.DuringanAUTO REFRESHcommand,addressbitsare"Don'tCare".This commandcorrespondstoCBRAuto-refresh.
WRITE
A burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank, and the starting column location is provided by inputs A0-A7.Whether or not AUTO-PRECHARGE is used is determined by A10. Therowbeingaccessedwillbeprechargedattheendof theWRITE burst, if AUTO PRECHARGE is selected. If AUTOPRECHARGEisnotselected,therowwillremain openforsubsequentaccesses. A memory array is written with corresponding input data onDQ'sandDQMinputlogiclevelappearingatthesame time.DatawillbewrittentomemorywhenDQMsignalis LOW.WhenDQMisHIGH,thecorrespondingdatainputs willbeignored,andaWRITEwillnotbeexecutedtothat byte/column location.
SELF REFRESH
DuringtheSELFREFRESHoperation,therowaddressto be refreshed, the bank, and the refresh interval are generatedautomaticallyinternally.SELFREFRESHcanbe usedtoretaindataintheSDRAMwithoutexternalclocking, eveniftherestofthesystemispowereddown.TheSELF REFRESHoperationisstartedbydroppingtheCKEpin fromHIGHtoLOW.DuringtheSELFREFRESHoperation allotherinputstotheSDRAMbecome"Don'tCare".The device must remain in self refresh mode for a minimum periodequaltotras or may remain in self refresh mode foranindefiniteperiodbeyondthat.TheSELF-REFRESH operationcontinuesaslongastheCKEpinremainsLOW andthereisnoneedforexternalcontrolofanyotherpins. Thenextcommandcannotbeexecuteduntilthedevice internal recovery period (trc) has elapsed. Once CKE goesHIGH,theNOPcommandmustbeissued(minimum of two clocks) to provide time for the completion of any internal refresh in progress. After the self-refresh, since it is impossible to determine the address of the last row to berefreshed,anAUTO-REFRESHshouldimmediatelybe performed for all addresses.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. BA0,BA1canbeusedtoselectwhichbankisprecharged or they are treated as "Don't Care". A10 determined whether one or all banks are precharged. After executing this command, the next command for the selected banks(s)isexecutedafterpassageoftheperiodtRP, which istheperiodrequiredforbankprecharging.Onceabank has been precharged, it is in the idle state and must be activatedpriortoanyREADorWRITEcommandsbeing issued to that bank.
BURST TERMINATE
The BURSTTERMINATE command forcibly terminates the burst read and write operations by truncating either fixed-length or full-page bursts and the most recently registeredREADorWRITEcommandpriortotheBURST TERMINATE.
AUTO PRECHARGE
TheAUTOPRECHARGEfunctionensuresthattheprecharge is initiated at the earliest valid stage within a burst. Thisfunctionallowsforindividual-bankprechargewithout requiringanexplicitcommand.A10toenablestheAUTO PRECHARGEfunctioninconjunctionwithaspecificREAD orWRITEcommand.ForeachindividualREADorWRITE command, auto precharge is either enabled or disabled.
COMMAND INHIBIT
COMMANDINHIBITpreventsnewcommandsfrombeing executed.Operationsinprogressarenotaffected,apart fromwhethertheCLKsignalisenabled
NO OPERATION
WhenCSislow,theNOPcommandpreventsunwanted commands from being registered during idle or wait states. Integrated Silicon Solution, Inc. -- www.issi.com
6
Rev. B 07/23/09
IS42S32200E, IS45S32200E
LOAD MODE REGISTER
DuringtheLOADMODEREGSITERcommandthemode registerisloadedfromA0-A10.Thiscommandcanonly be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1 inputs selects a bank to be accessed, and the address inputsonA0-A10selectstherow.UntilaPRECHARGE command is issued to the bank, the row remains open for accesses.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
7
IS42S32200E, IS45S32200E
TRUTH TABLE - COMMANDS AND DQM OPERATION(1)
FUNCTION CS COMMANDINHIBIT(NOP) H NOOPERATION(NOP) L ACTIVE(Selectbankandactivaterow)(3) L (4) READ(Selectbank/column,startREADburst) L (4) WRITE(Selectbank/column,startWRITEburst) L BURSTTERMINATE L PRECHARGE(Deactivaterowinbankorbanks)(5) L AUTOREFRESHorSELFREFRESH(6,7) L (Enterselfrefreshmode) LOADMODEREGISTER(2) L (8) WriteEnable/OutputEnable -- WriteInhibit/OutputHigh-Z(8) -- RAS X H L H H H L L L -- -- CAS X H H L L H H L L -- -- WE X H H H L L L H L -- -- DQM X X X L/H(8) L/H(8) X X X X L H ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code -- -- DQs X X X X Valid Active X X X Active High-Z
NOTES: 1. CKEisHIGHforallcommandsexceptSELFREFRESH. 2. A0-A10 define the op-code written to the mode register. 3. A0-A10providerowaddress,andBA0,BA1determinewhichbankismadeactive. 4. A0-A7(x32)providecolumnaddress;A10HIGHenablestheautoprechargefeature(nonpersistent),whileA10LOWdisables autoprecharge;BA0,BA1determinewhichbankisbeingreadfromorwrittento. 5. A10LOW:BA0,BA1determinethebankbeingprecharged.A10HIGH:AllbanksprechargedandBA0,BA1are"Don'tCare." 6. AUTOREFRESHifCKEisHIGH,SELFREFRESHifCKEisLOW. 7. Internalrefreshcountercontrolsrowaddressing;allinputsandDQsare"Don'tCare"exceptforCKE. 8. ActivatesordeactivatestheDQsduringWRITEs(zero-clockdelay)andREADs(two-clockdelay).
8
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
TRUTH TABLE - CKE (1-4)
CURRENT STATE Power-Down SelfRefresh ClockSuspend Power-Down(5) SelfRefresh(6) Clock Suspend(7) AllBanksIdle AllBanksIdle ReadingorWriting COMMANDn X X X COMMANDINHIBITorNOP COMMANDINHIBITorNOP X COMMANDINHIBITorNOP AUTOREFRESH VALID ACTIONn MaintainPower-Down MaintainSelfRefresh MaintainClockSuspend ExitPower-Down ExitSelfRefresh ExitClockSuspend Power-DownEntry SelfRefreshEntry ClockSuspendEntry CKEn-1 L L L L L L H H H H CKEn L L L H H H L L L H
See TRUTH TABLE - CURRENT STATE BANK n, COMMAND TO BANK n
NOTES: 1. CKEnisthelogicstateofCKEatclockedgen;CKEn-1 wasthestateofCKEatthepreviousclockedge. 2. CurrentstateisthestateoftheSDRAMimmediatelypriortoclockedgen. 3. COMMANDnisthecommandregisteredatclockedgen,andACTONnisaresultofCOMMANDn. 4. Allstatesandsequencesnotshownareillegalorreserved. 5. Exitingpower-downatclockedgen will put the device in the all banks idle state in time for clock edge n+1 (provided that tcks is met). 6. Exitingselfrefreshatclockedgen will put the device in all banks idle state once txsrismet.COMMANDINHIBITorNOP commands should be issued on clock edges occurring during the txsrperiod.AminimumoftwoNOPcommandsmustbesent during txsr period. 7. Afterexitingclocksuspendatclockedgen,thedevicewillresumeoperationandrecognizethenextcommandatclockedge n+1.
TRUTH TABLE - CURRENT STATE BANK n, COMMAND TO BANK n (1-6)
CURRENTSTATE Any Idle RowActive Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) COMMAND(ACTION) COMMANDINHIBIT(NOP/Continuepreviousoperation) NOOPERATION(NOP/Continuepreviousoperation) ACTIVE(Selectandactivaterow) AUTOREFRESH(7) LOADMODEREGISTER(7) PRECHARGE(11) READ(SelectcolumnandstartREADburst)(10) WRITE(SelectcolumnandstartWRITEburst)(10) PRECHARGE(Deactivaterowinbankorbanks)(8) READ(SelectcolumnandstartnewREADburst)(10) WRITE(SelectcolumnandstartWRITEburst)(10) PRECHARGE(TruncateREADburst,startPRECHARGE)(8) BURSTTERMINATE(9) READ(SelectcolumnandstartREADburst)(10) WRITE(SelectcolumnandstartnewWRITEburst)(10) PRECHARGE(TruncateWRITEburst,startPRECHARGE)(8) BURSTTERMINATE(9) CS RAS CAS WE H X X X L H H H L L H H L L L H L L L L L L H L L H L H L H L L L L H L L H L H L H L L L L H L L H H L L H L H L H L L L L H L L H H L
NOTE: 1.ThistableapplieswhenCKEn-1wasHIGHandCKEnisHIGH(seeTruthTable-CKE)andaftertxsr has been met (if the previous state was SELFREFRESH). 2.Thistableisbank-specific,exceptwherenoted;i.e.,thecurrentstateisforaspecificbankandthecommandsshownarethose allowedtobeissuedtothatbankwheninthatstate.Exceptionsarecoveredinthenotesbelow.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
9
IS42S32200E, IS45S32200E
3.Currentstatedefinitions: Idle:Thebankhasbeenprecharged,andtrp has been met. RowActive:Arowinthebankhasbeenactivated,andtrcd has been met. No data bursts/accesses and no register accesses are in progress. Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated. Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated. 4.Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.COMMANDINHIBITorNOPcommands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commandstotheotherbankaredeterminedbyitscurrentstateandCURRENTSTATEBANKntruthtables. Precharging:StartswithregistrationofaPRECHARGEcommandandendswhentrpismet.Oncetrp is met, the bank will be in the idle state. RowActivating:StartswithregistrationofanACTIVEcommandandendswhentrcdismet.Oncetrcd is met, the bank will be in the row active state. Readw/Auto PrechargeEnabled:StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhentrp has been met.Oncetrp is met, the bank will be in the idle state. Writew/Auto PrechargeEnabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhentrp has been met.Oncetrp is met, the bank will be in the idle state. 5.Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;COMMANDINHIBITorNOPcommandsmustbe applied on each positive clock edge during these states. Refreshing:StartswithregistrationofanAUTOREFRESHcommandandendswhentrcismet.Oncetrc is met, the SDRAMwillbeintheallbanksidlestate. AccessingMode Register:StartswithregistrationofaLOADMODEREGISTERcommandandendswhentmrdhasbeenmet.Once tmrdismet,theSDRAMwillbeintheallbanksidlestate. PrechargingAll:StartswithregistrationofaPRECHARGEALLcommandandendswhentrpismet.Oncetrp is met, all banks will be in the idle state. 6.Allstatesandsequencesnotshownareillegalorreserved. 7.Notbank-specific;requiresthatallbanksareidle. 8.Mayormaynotbebank-specific;ifallbanksaretobeprecharged,allmustbeinavalidstateforprecharging. 9.Notbank-specific;BURSTTERMINATEaffectsthemostrecentREADorWRITEburst,regardlessofbank. 10.READsorWRITEslistedintheCommand(Action)columnincludeREADsorWRITEswithautoprechargeenabledand READsorWRITEswithautoprechargedisabled. 11.DoesnotaffectthestateofthebankandactsasaNOPtothatbank.
10
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
TRUTH TABLE - CURRENT STATE BANK n, COMMAND TO BANK m (1-6)
CURRENTSTATE Any Idle Row Activating, Active,or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (WithAuto Precharge) Write (WithAuto Precharge) COMMAND(ACTION) COMMANDINHIBIT(NOP/Continuepreviousoperation) NOOPERATION(NOP/Continuepreviousoperation) AnyCommandOtherwiseAllowedtoBankm ACTIVE(Selectandactivaterow) READ(SelectcolumnandstartREADburst)(7) WRITE(SelectcolumnandstartWRITEburst)(7) PRECHARGE ACTIVE(Selectandactivaterow) READ(SelectcolumnandstartnewREADburst)(7,10) WRITE(SelectcolumnandstartWRITEburst)(7,11) PRECHARGE(9) ACTIVE(Selectandactivaterow) READ(SelectcolumnandstartREADburst)(7,12) WRITE(SelectcolumnandstartnewWRITEburst) PRECHARGE(9) ACTIVE(Selectandactivaterow) READ(SelectcolumnandstartnewREADburst)(7,8,14) WRITE(SelectcolumnandstartWRITEburst)(7,8,15) PRECHARGE(9) ACTIVE(Selectandactivaterow) READ(SelectcolumnandstartREADburst)(7,8,16) WRITE(SelectcolumnandstartnewWRITEburst)(7,8,17) PRECHARGE(9)
(7,13)
CS RAS CAS WE H X X X L H H H X X X X L L H H L H L H L H L L L L H L L L H H L H L H L H L L L L H L L L H H L L L L L L L L L L L H H L L H H L L H H L L L H H L L H H L L H H L L H H L L H H L L
NOTE: 1.ThistableapplieswhenCKEn-1wasHIGHandCKEnisHIGH(TruthTable-CKE)andaftertxsr has been met (if the previousstatewasselfrefresh). 2.Thistabledescribesalternatebankoperation,exceptwherenoted;i.e.,thecurrentstateisforbankn and the commands shown are those allowed to be issued to bank m (assuming that bank m isinsuchastatethatthegivencommandisallowable).Exceptions are covered in the notes below. 3.Currentstatedefinitions: Idle:Thebankhasbeenprecharged,andtrp has been met. RowActive:Arowinthebankhasbeenactivated,andtrcd has been met. No data bursts/accesses and no register accesses are in progress. Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated. Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeenterminated. Readw/Auto PrechargeEnabled:StartswithregistrationofaREADcommandwithautoprechargeenabled,andendswhentrp has been met.Oncetrp is met, the bank will be in the idle state. Writew/Auto PrechargeEnabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabled,andendswhentrp has been met.Oncetrp is met, the bank will be in the idle state. 4.AUTOREFRESH,SELFREFRESHandLOADMODEREGISTERcommandsmayonlybeissuedwhenallbanksareidle. 5.ABURSTTERMINATEcommandcannotbeissuedtoanotherbank;itappliestothebankrepresentedbythecurrentstate only. 6.Allstatesandsequencesnotshownareillegalorreserved. 7.READsorWRITEstobankmlistedintheCommand(Action)columnincludeREADsorWRITEswithautoprechargeenabled andREADsorWRITEswithautoprechargedisabled.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
11
IS42S32200E, IS45S32200E
8.CONCURRENTAUTOPRECHARGE:BanknwillinitiatetheAUTOPRECHARGEcommandwhenitsbursthasbeeninterruptedbybankm'sburst. 9.Burstinbankncontinuesasinitiated. 10.ForaREADwithoutautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupt theREADonbankn,CASlatencylater(ConsecutiveREADBursts). 11.ForaREADwithoutautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupttheREADonbanknwhenregistered(READtoWRITE).DQMshouldbeusedoneclockpriortotheWRITEcommandto prevent bus contention. 12.ForaWRITEwithoutautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupt theWRITEonbanknwhenregistered(WRITEtoREAD),withthedata-outappearingCASlatencylater.ThelastvalidWRITE tobanknwillbedata-inregisteredoneclockpriortotheREADtobankm. 13.ForaWRITEwithoutautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupttheWRITEonbanknwhenregistered(WRITEtoWRITE).ThelastvalidWRITEtobanknwillbedata-inregisteredone clockpriortotheREADtobankm. 14.ForaREADwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterruptthe READonbankn,CASlatencylater.ThePRECHARGEtobanknwillbeginwhentheREADtobankmisregistered(FigCAP 1). 15.ForaREADwithautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupt theREADonbanknwhenregistered.DQMshouldbeusedtwoclockspriortotheWRITEcommandtopreventbuscontention. ThePRECHARGEtobanknwillbeginwhentheWRITEtobankmisregistered(FigCAP2). 16.ForaWRITEwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupt theWRITEonbanknwhenregistered,withthedata-outappearingCASlatencylater.ThePRECHARGEtobanknwillbegin after tWR is met, where twrbeginswhentheREADtobankmisregistered.ThelastvalidWRITEtobanknwillbedata-inregisteredoneclockpriortotheREADtobankm(FigCAP3). 17.ForaWRITEwithautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupt theWRITEonbanknwhenregistered.ThePRECHARGEtobanknwillbeginaftertwrismet,wheretWRbeginswhenthe WRITEtobankmisregistered.ThelastvalidWRITEtobanknwillbedataregisteredoneclockpriortotheWRITEtobankm (FigCAP4).
12
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
FUNCTIONAL DESCRIPTION
The64MbSDRAMs512Kx32x4banks)arequad-bank DRAMswhichoperateat3.3Vandincludeasynchronous interface (all signals are registered on the positive edge of theclocksignal,CLK).Eachofthe16,777,216-bitbanksis organizedas2,048rowsby256columnsby32bits. ReadandwriteaccessestotheSDRAMareburstoriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.AccessesbeginwiththeregistrationofanACTIVEcommandwhichisthenfollowedbyaREADorWRITE command.Theaddressbitsregisteredcoincidentwiththe ACTIVEcommandareusedtoselectthebankandrowto be accessed (BA0andBA1selectthebank,A0-A10selectthe row).Theaddressbits(A0-A7) registered coincident with the READorWRITEcommandareusedtoselectthestarting column location for the burst access. Prior to normal operation, the SDRAM must be initialized.Thefollowingsectionsprovidedetailedinformation coveringdeviceinitialization,registerdefinition,command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. The64MSDRAMisinitializedafterthepowerisappliedto VddandVddq(simultaneously)andtheclockisstable. A100sdelayisrequiredpriortoissuinganycommand other than a COMMANDINHIBIT or a NOP.TheCOMMAND INHIBITorNOPmaybeappliedduringthe100usperiodand continue should at least through the end of the period. WithatleastoneCOMMANDINHIBITorNOPcommand havingbeenapplied,aPRECHARGEcommandshould be applied once the 100s delay has been satisfied. All banks must be precharged. This will leave all banks in an idle idle state where two AUTO REFRESH cycles must be performed. After the AUTOREFRESH cycles are complete,theSRDRAMisthenreadyformoderegister programming. The mode register should be loaded prior to applying any operational command because it will power up in an unknown state.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
13
IS42S32200E, IS45S32200E
REGISTER DEFINITION Mode Register
The mode register is used to define the specific mode ofoperationoftheSDRAM.Thisdefinitionincludesthe selection of a burst length, a burst type, a CAS\ latency, an operating mode and a write burst mode, as shown in MODEREGISTERDEFINITION. ThemoderegisterisprogrammedviatheLOADMODE REGISTERcommandandwillretainthestoredinformation until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequentialorinterleaved),M4-M6 specifytheCASlatency,M7andM8specifytheoperating mode,M9specifiestheWRITEburstmode,andM10and M11andM12arereservedforfutureuse. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiatingthesubsequentoperation.Violatingeitherofthese requirementswillresultinunspecifiedoperation.
MODE REGISTER DEFINITION
BA0,1
(1)
A10/AP
(1)
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
0
Burst Type M3Type 0 1 Sequential Interleaved Burst Length M2 M1 M0 0 0 0 0 1 1 1 1 Latency Mode M6 M5 M4 0 0 0 0 1 1 1 1 MRS M8 M7 0 -- 0 -- MRS Mode Register Set All Other States Reserved 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sequential 1 2 4 8 Reserved Reserved Reserved Full Page Interleave 1 2 4 8 Reserved Reserved Reserved Reserved
Write Burst Mode M9 0 1 Mode Burst Write Single-Bit Write
Note: 1. Maintain low during Mode Register Set.
14
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
Burst Length
ReadandwriteaccessestotheSDRAMareburstoriented, with the burst length being programmable, as shown in MODEREGISTERDEFINITION.Theburstlengthdeterminesthemaximumnumberofcolumnlocationsthatcan beaccessedforagivenREADorWRITEcommand.Burst lengthsof1,2,4or8locationsareavailableforboththe sequentialandtheinterleavedbursttypes,andafull-page burst is available for the sequential type.The full-page burstisusedinconjunctionwiththeBURSTTERMINATE command to generate arbitrary burst lengths. Reservedstatesshouldnotbeused,asunknownoperation or incompatibility with future versions may result. WhenaREADorWRITEcommandisissued,ablockof columnsequaltotheburstlengthiseffectivelyselected.All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary isreached.TheblockisuniquelyselectedbyA1-A7(x32) whentheburstlengthissettotwo;byA2-A7(x32)when theburstlengthissettofour;andbyA3-A7(x32)whenthe burstlengthissettoeight.Theremaining(leastsignificant) addressbit(s)is(are)usedtoselectthestartinglocation withintheblock.Full-pageburstswrapwithinthepageif the boundary is reached.
BurstType
Accesses within a given burst may be programmed to be eithersequentialorinterleaved;thisisreferredtoasthe bursttypeandisselectedviabitM3. Theorderingofaccesseswithinaburstisdeterminedby the burst length, the burst type and the starting column address,asshowninBURSTDEFINITIONtable.
BURST DEFINITION
Burst Length 2 Starting Column Address A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n=A0-A7 (location0-y) Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn,Cn+1,Cn+2 Cn+3,Cn+4... ...Cn-1, Cn... 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 NotSupported
4
8 Full Page (y)

Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
15
IS42S32200E, IS45S32200E
CAS Latency
The CAS latency is the delay, in clock cycles, between the registrationofaREADcommandandtheavailabilityof thefirstpieceofoutputdata.Thelatencycanbesettotwoor three clocks. IfaREADcommandisregisteredatclockedgen,and the latency is m clocks, the data will be available by clock edge n + m.TheDQswillstartdrivingasaresultofthe clock edge one cycle earlier (n + m -1),andprovidedthat the relevant access times are met, the data will be valid by clock edge n + m.Forexample,assumingthattheclock cycle time is such that all relevant access times are met, ifaREADcommandisregisteredatT0andthelatency isprogrammedtotwoclocks,theDQs willstartdriving afterT1andthedatawillbevalidbyT2,asshowninCAS Latencydiagrams.TheAllowable Operating Frequency tableindicatestheoperatingfrequenciesatwhicheach CAS latency setting can be used. Reservedstatesshouldnotbeusedasunknownoperation or incompatibility with future versions may result.
Operating Mode
ThenormaloperatingmodeisselectedbysettingM7andM8 tozero;theothercombinationsofvaluesforM7andM8are reservedforfutureuseand/ortestmodes.Theprogrammed burstlengthappliestobothREADandWRITEbursts. Testmodesandreservedstatesshouldnotbeusedbecause unknown operation or incompatibility with future versions may result.
Write Burst Mode
WhenM9=0,theburstlengthprogrammedviaM0-M2 appliestobothREADandWRITEbursts;whenM9=1, theprogrammedburstlengthappliestoREADbursts,but writeaccessesaresingle-location(nonburst)accesses.
CAS Latency Allowable Operating Frequency (MHz)
Speed -5 -6 -7 -75E CAS Latency = 2 100 100 100 133 CAS Latency = 3 200 166 143 -
CAS Latency
T0 CLK T1 T2 T3
COMMAND DQ
READ
NOP tAC
NOP DOUT
tLZ CAS Latency - 2
tOH
T0 CLK
T1
T2
T3
T4
COMMAND DQ
READ
NOP
NOP tAC
NOP DOUT
tLZ CAS Latency - 3
tOH DON'T CARE UNDEFINED
16
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
OPERATION BANK/ROW ACTIVATION
Before any READ orWRITE commands can be issued toabankwithintheSDRAM,arowinthatbankmustbe "opened."ThisisaccomplishedviatheACTIVEcommand, which selects both the bank and the row to be activated (see ActivatingSpecificRowWithinSpecificBank). After opening a row (issuinganACTIVEcommand),aREAD orWRITEcommandmaybeissuedtothatrow,subjectto the trcdspecification.Minimumtrcd should be divided by theclockperiodandroundeduptothenextwholenumber to determine the earliest clock edge after the ACTIVE commandonwhichaREADorWRITEcommandcanbe entered.Forexample,atrcd specification of 20ns with a 125MHzclock(8nsperiod)resultsin2.5clocks,rounded to3.Thisisreflectedinthefollowingexample,whichcovers any case where 2 < [trcd(MIN)/tck] 3.(Thesame procedure is used to convert other specification limits from timeunitstoclockcycles). AsubsequentACTIVEcommandtoadifferentrowinthe same bank can only be issued after the previous active rowhasbeen"closed"(precharged).Theminimumtime interval between successive ACTIVE commands to the same bank is defined by trc. AsubsequentACTIVEcommandtoanotherbankcanbe issued while the first bank is being accessed, which results inareductionoftotalrow-accessoverhead.Theminimum timeintervalbetweensuccessiveACTIVEcommandsto different banks is defined by trrd.
Activating Specific Row Within Specific Bank
CLK CKE CS RAS CAS WE A0-A10 BA0, BA1 ROW ADDRESS BANK ADDRESS HIGH - Z
Example: Meeting tRCD (MIN) when 2 < [tRCD (min)/tCK] 3
T0 CLK
T1
T2
T3
T4
COMMAND
ACTIVE
NOP tRCD
NOP
READ or WRITE
DON'T CARE
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
17
IS42S32200E, IS45S32200E
READS
READ bursts are initiated with a READ command, as shownintheREADCOMMANDdiagram. Thestartingcolumnandbankaddressesareprovidedwith theREADcommand,andautoprechargeiseitherenabledor disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of theburst.ForthegenericREADcommandsusedinthefollowing illustrations, auto precharge is disabled. DuringREADbursts,thevaliddata-outelementfromthe starting column address will be available following the CASlatencyaftertheREADcommand.Eachsubsequent data-outelementwillbevalidbythenextpositiveclock edge.The CAS Latency diagram shows general timing for each possible CAS latency setting. Uponcompletionofaburst,assumingnoothercommands havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst will continue until terminated. (At the end of the page, it will wraptocolumn0andcontinue.) DatafromanyREADburstmaybetruncatedwithasubsequentREADcommand,anddatafromafixed-length READburstmaybeimmediatelyfollowedbydatafroma READcommand.Ineithercase,acontinuousflowofdata canbemaintained.Thefirstdataelementfromthenew burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. ThenewREADcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equalstheCASlatencyminusone.Thisis showninConsecutiveREADBurstsforCASlatenciesof twoandthree;dataelementn + 3 is either the last of a burstoffourorthelastdesiredofalongerburst.The64Mb SDRAMusesapipelinedarchitectureandthereforedoes notrequirethe2n rule associated with a prefetch architecture.AREADcommandcanbeinitiatedonanyclockcycle followingapreviousREADcommand.Full-speedrandom read accesses can be performed to the same bank, as showninRandomREADAccesses,oreachsubsequent READmaybeperformedtoadifferentbank. DatafromanyREADburstmaybetruncatedwithasubsequent WRITE command, and data from a fixed-length READburstmaybeimmediatelyfollowedbydatafroma WRITEcommand(subjecttobusturnaroundlimitations). TheWRITEburstmaybeinitiatedontheclockedgeimmediatelyfollowingthelast(orlastdesired)dataelement fromtheREADburst,providedthatDQcontentioncanbe avoided. In a given system design, there may be a possibilitythatthedevicedrivingtheinputdatawillgoLow-Z beforetheSDRAMDQsgoHigh-Z.Inthiscase,atleast a single-cycle delay should occur between the last read dataandtheWRITEcommand. 18
READ COMMAND
CLK CKE CS RAS CAS WE A0-A7 A8, A9
AUTO PRECHARGE COLUMN ADDRESS HIGH-Z
A10
NO PRECHARGE
BA0, BA1
BANK ADDRESS
TheDQMinputisusedtoavoidDQcontention,asshownin FiguresRW1andRW2.TheDQMsignalmustbeasserted (HIGH)atleasttwoclockspriortotheWRITEcommand (DQMlatencyistwoclocksforoutputbuffers)tosuppress data-outfromtheREAD.OncetheWRITEcommandis registered, the DQs will go High-Z (or remain High-Z), regardlessofthestateoftheDQMsignal,providedthe DQM was active on the clock just prior to the WRITE commandthattruncatedtheREADcommand.Ifnot,the secondWRITEwillbeaninvalidWRITE.Forexample,if DQMwasLOWduringT4inFigureRW2,thentheWRITEs atT5andT7wouldbevalid,whiletheWRITEatT6would be invalid. TheDQMsignalmustbede-assertedpriortotheWRITE command(DQMlatencyiszeroclocksforinputbuffers) toensurethatthewrittendataisnotmasked.FigureRW1 showsthecasewheretheclockfrequencyallowsforbus contention to be avoided without adding a NOP cycle, and Figure RW2 shows the case where the additional NOPisneeded. Afixed-lengthREADburstmaybefollowedby,ortruncated with, a PRECHARGE command to the same bank (provided thatautoprechargewasnotactivated), and a full-page burst maybetruncatedwithaPRECHARGEcommandtothe
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
samebank.ThePRECHARGEcommandshouldbeissued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minusone.ThisisshownintheREADtoPRECHARGE diagramforeachpossibleCASlatency;dataelementn + 3 is either the last of a burst of four or the last desired of alongerburst.FollowingthePRECHARGEcommand,a subsequentcommandtothesamebankcannotbeissued until trp is met. Note that part of the row precharge time is hiddenduringtheaccessofthelastdataelement(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burstwithautoprecharge.ThedisadvantageofthePRECHARGEcommandisthatitrequiresthatthecommand and address buses be available at the appropriate time to issuethecommand;theadvantageofthePRECHARGE commandisthatitcanbeusedtotruncatefixed-length or full-page bursts. Full-pageREADburstscanbetruncatedwiththeBURST TERMINATE command, and fixed-length READ bursts maybetruncatedwithaBURSTTERMINATEcommand, providedthatautoprechargewasnotactivated.TheBURST TERMINATEcommandshouldbeissuedx cycles before the clock edge at which the last desired data element is valid, where x equalstheCASlatencyminusone.Thisis shownintheREADBurstTerminationdiagramforeach possibleCASlatency;dataelementn + 3 is the last desired data element of a longer burst.
CAS Latency
T0 CLK
T1
T2
T3
COMMAND DQ
READ
NOP tAC
NOP DOUT
tLZ CAS Latency - 2
tOH
T0 CLK
T1
T2
T3
T4
COMMAND DQ
READ
NOP
NOP tAC
NOP DOUT
tLZ CAS Latency - 3
tOH DON'T CARE UNDEFINED
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
19
IS42S32200E, IS45S32200E
Consecutive READ Bursts
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
READ x =1 cycle
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ CAS Latency - 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b DON'T CARE
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
READ
NOP x = 2 cycles
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ CAS Latency - 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b DON'T CARE
20
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
Random READ Accesses
T0 CLK
T1
T2
T3
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
BANK, COL m
BANK, COL x
DQ CAS Latency - 2
DOUT n
DOUT b
DOUT m
DOUT x DON'T CARE
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
BANK, COL m
BANK, COL x
DQ CAS Latency - 3
DOUT n
DOUT b
DOUT m
DOUT x DON'T CARE
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
21
IS42S32200E, IS45S32200E
RW1 - READ to WRITE
T0 CLK
T1
T2
T3
T4
DQM
COMMAND
READ
NOP
NOP
NOP
WRITE
ADDRESS
BANK, COL n
BANK, COL b
DQ CAS Lantency 3
tHZ DOUT n
DIN b tDS DON'T CARE
RW2 - READ to WRITE With Extra Clock Cycle
T0 CLK
T1
T2
T3
T4
T5
DQM
COMMAND
READ
NOP
NOP
NOP
NOP
WRITE
ADDRESS
BANK, COL n
BANK, COL b
DQ
tHZ DOUT n
DIN b tDS
CAS Lantency 3
DON'T CARE
22
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
READ to PRECHARGE
T0 CLK
T1
T2
T3
T4
T5 tRP
T6
T7
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
x = 1 cycle
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ CAS Latency - 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3 DON'T CARE
T0 CLK
T1
T2
T3
T4
T5 tRP
T6
T7
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP x = 2 cycles
NOP
ACTIVE
ADDRESS
BANK, COL n
BANK, COL b
BANK a, ROW
DQ CAS Latency - 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3 DON'T CARE
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
23
IS42S32200E, IS45S32200E
READ Burst Termination
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE
NOP
NOP
x = 1 cycle
ADDRESS
BANK a, COL n
DQ CAS Latency - 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3 DON'T CARE
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE
NOP x = 2 cycles
NOP
NOP
ADDRESS
BANK, COL n
DQ CAS Latency - 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3 DON'T CARE
24
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
WRITEs
WRITEburstsareinitiatedwithaWRITEcommand,as showninWRITECommanddiagram. AnexampleisshowninWRITEtoWRITEdiagram.Data n + 1 is either the last of a burst of two or the last desired of a longer burst.The 64Mb SDRAM uses a pipelined architectureandthereforedoesnotrequirethe2n rule associatedwithaprefetcharchitecture.AWRITEcommand can be initiated on any clock cycle following a previous WRITEcommand.Full-speedrandomwriteaccesseswithin a page can be performed to the same bank, as shown in RandomWRITECycles,oreachsubsequentWRITEmay be performed to a different bank. DataforanyWRITEburstmaybetruncatedwithasubsequentREADcommand,anddataforafixed-lengthWRITE burstmaybeimmediatelyfollowedbyasubsequentREAD command.OncetheREADcommandisregistered,the datainputswillbeignored,andWRITEswillnotbeexecuted.AnexampleisshowninWRITEtoREAD.Datan + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be fol lowed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-pageWRITE burst may be truncated with a PRECHARGE command to the same bank.The PRECHARGEcommandshouldbeissuedtwr after the clock edge at which the last desired input data element isregistered.Theautoprechargemoderequiresatwr of atleastoneclockplustime,regardlessoffrequency.In addition,whentruncatingaWRITEburst,theDQMsignal must be used to mask input data for the clock edge prior to,andtheclockedgecoincidentwith,thePRECHARGE command.AnexampleisshownintheWRITEtoPRECHARGEdiagram.Datan+1 is either the last of a burst oftwoorthelastdesiredofalongerburst.Followingthe PRECHARGEcommand,asubsequentcommandtothe same bank cannot be issued until trp is met. Inthecaseofafixed-lengthburstbeingexecutedtocompletion, a PRECHARGE command issued at the optimum time (asdescribedabove) provides the same operation that wouldresultfromthesamefixed-lengthburstwithauto precharge.ThedisadvantageofthePRECHARGE command isthatitrequiresthatthecommandandaddressbusesbe availableattheappropriatetimetoissuethecommand;the advantageofthePRECHARGEcommandisthatitcanbe usedtotruncatefixed-lengthorfull-pagebursts. Fixed-lengthorfull-pageWRITEburstscanbetruncated withtheBURSTTERMINATEcommand.WhentruncatingaWRITEburst,theinputdataappliedcoincidentwith theBURSTTERMINATEcommandwillbeignored.The lastdatawritten(providedthatDQMisLOWatthattime) will be the input data applied one clock previous to the BURSTTERMINATEcommand.ThisisshowninWRITE BurstTermination,wheredatan is the last desired data element of a longer burst. 25
WRITE Command
CLK CKE CS RAS CAS WE A0-A7 A8, A9
AUTO PRECHARGE COLUMN ADDRESS HIGH - Z
A10
NO PRECHARGE
BA0, BA1
BANK ADDRESS
Thestartingcolumnandbankaddressesareprovidedwith theWRITEcommand,andautoprechargeiseitherenabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of theburst.ForthegenericWRITEcommandsusedinthe following illustrations, auto precharge is disabled. DuringWRITEbursts,thefirstvaliddata-in element will be registered coincident with the WRITEcommand.Subsequent data elements will be registered on each successive positiveclockedge.Uponcompletionofafixed-lengthburst, assuming no other commands have been initiated, the DQswillremainHigh-Zandanyadditionalinputdatawill beignored(seeWRITEBurst).Afull-pageburstwillcontinue until terminated. (At the end of the page, it will wrap tocolumn0andcontinue.) DataforanyWRITEburstmaybetruncatedwithasubsequentWRITEcommand,anddataforafixed-lengthWRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on anyclockfollowingthepreviousWRITEcommand,andthe data provided coincident with the new command applies to the new command. Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
WRITE Burst
T0 CLK T1 T2 T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK, COL n
DQ
DIN n
DIN n+1 DON'T CARE
Burst length = 2 DQM ix low.
WRITE to WRITE
T0 CLK T1 T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK, COL n
BANK, COL b
DQ
DIN n
DIN n+1
DIN b DON'T CARE
DQMx is low. Each Write Command may be to any bank.
Random WRITE Cycles
T0 CLK T1 T2 T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK, COL n
BANK, COL b
BANK, COL m
BANK, COL x
DQ
DIN n
DIN b
DIN m
DIN x
DQMx is low. Each Write Command may be to any bank. 26 Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
WRITE to READ
T0 CLK T1 T2 T3 T4 T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ
DIN n
DIN n+1
DOUT b
DOUT b+1 DON'T CARE
WRITE to PRECHARGE (twr = 1CLK(tck twr)
T0 CLK T1 T2 T3 T4 T5 T6
DQM tRP COMMAND WRITE NOP
PRECHARGE
NOP
NOP
ACTIVE
NOP
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
tWR DQ DIN n DIN n+1 DON'T CARE
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
27
IS42S32200E, IS45S32200E
WRITE to PRECHARGE (twr = 2CLK(twr > tck)
T0 CLK T1 T2 T3 T4 T5 T6
DQM tRP COMMAND WRITE NOP NOP
PRECHARGE
NOP
NOP
ACTIVE
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
tWR DQ DIN n DIN n+1 DON'T CARE
WRITE Burst Termination
T0 CLK T1 T2
COMMAND
WRITE
BURST TERMINATE
NEXT COMMAND
ADDRESS
BANK, COL n
(ADDRESS)
DQ
DIN n
(DATA) DON'T CARE
28
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
PRECHARGE
ThePRECHARGEcommand(seefigure)isusedtodeactivate the open row in a particular bank or the open row in allbanks.Thebank(s)willbeavailableforasubsequentrow access some specified time (trp)afterthePRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only onebankistobeprecharged,inputsBA0,BA1selectthe bank.Whenallbanksaretobeprecharged,inputsBA0, BA1aretreatedas"Don'tCare."Onceabankhasbeen precharged, it is in the idle state and must be activated priortoanyREADorWRITEcommandsbeingissuedto that bank.
PRECHARGE Command
CLK CKE CS RAS CAS WE A0-A9
ALL BANKS HIGH - Z
POWER-DOWN
Power-downoccursifCKEisregisteredLOWcoincident withaNOPorCOMMANDINHIBITwhennoaccesses are in progress. If power-down occurs when all banks are idle,thismodeisreferredtoasprechargepower-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers,excludingCKE,formaximumpowersavingswhile instandby.Thedevicemaynotremaininthepower-down state longer than the refresh period (tref)sincenorefresh operations are performed in this mode. Thepower-downstateisexitedbyregisteringaNOPor COMMANDINHIBITandCKEHIGHatthedesiredclock edge (meeting tcks).Seefigurebelow.
A10
BANK SELECT
BA0, BA1
BANK ADDRESS
POWER-DOWN
CLK tCKS CKE tCKS
COMMAND
NOP Input buffers gated off
NOP
ACTIVE tRCD tRAS tRC DON'T CARE
All banks idle
Enter power-down mode
Exit power-down mode
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
29
IS42S32200E, IS45S32200E
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst isinprogressandCKEisregisteredLOW.Intheclock suspendmode,theinternalclockisdeactivated,"freezing" the synchronous logic. ForeachpositiveclockedgeonwhichCKEissampled LOW,thenextinternalpositiveclockedgeissuspended. Any command or data present on the input pins at the time ofasuspendedinternalclockedgeisignored;anydata presentontheDQpinsremainsdriven;andburstcounters are not incremented, as long as the clock is suspended. (Seefollowingexamples.) ClocksuspendmodeisexitedbyregisteringCKEHIGH; the internal clock and related operation will resume on the subsequentpositiveclockedge.
Clock Suspend During WRITE Burst
T0 CLK T1 T2 T3 T4 T5
CKE INTERNAL CLOCK COMMAND NOP WRITE NOP NOP
ADDRESS
BANK a, COL n
DQ
DIN n
DIN n+1
DIN n+2 DON'T CARE
Burst Length 4 or greater DQM is low.
Clock Suspend During READ Burst
T0 CLK T1 T2 T3 T4 T5 T6
CKE INTERNAL CLOCK COMMAND READ NOP NOP NOP NOP NOP
ADDRESS
BANK a, COL n
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3 DON'T CARE
CAS Latency=2. Burst Length =4 or greater. DQM is low. 30
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
BURST READ/SINGLE WRITE
Theburstread/singlewritemodeisenteredbyprogramming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access ofasinglecolumnlocation(burstofone),regardlessof theprogrammedburstlength.READcommandsaccess columns according to the programmed burst length and sequence,justasinthenormalmodeofoperation(M9 =0). SDRAMssupportCONCURRENTAUTOPRECHARGE. FourcaseswhereCONCURRENTAUTOPRECHARGE occurs are defined below.
READ with Auto Precharge
1.InterruptedbyaREAD(withorwithoutautoprecharge): AREADtobankmwillinterruptaREADonbankn, CAS latency later.The PRECHARGE to bank n will beginwhentheREADtobankmisregistered. 2.InterruptedbyaWRITE(withorwithoutautoprecharge): AWRITEtobankmwillinterruptaREADonbankn whenregistered.DQMshouldbeusedtwoclocksprior totheWRITEcommandtopreventbuscontention.The PRECHARGEtobanknwillbeginwhentheWRITEto bank m is registered.
CONCURRENT AUTO PRECHARGE
Anaccesscommand(READorWRITE)toanotherbank while an access command with auto precharge enabled is executingisnotallowedbySDRAMs,unlesstheSDRAM supports CONCURRENT AUTO PRECHARGE. ISSI
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
T0 CLK COMMAND BANK n NOP
READ - AP BANK n
T1
T2
T3
T4
T5
T6
T7
NOP
READ - AP BANK m
NOP
NOP
NOP
NOP
Page Active
READ with Burst of 4
Interrupt Burst, Precharge tRP - BANK n
Idle tRP - BANK m Precharge
Internal States
BANK m ADDRESS DQ CAS Latency - 3 (BANK n) Page Active
BANK n, COL a BANK m, COL b
READ with Burst of 4
DOUT a
DOUT a+1
DOUT b
DOUT b+1 DON'T CARE
CAS Latency - 3 (BANK m)
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
T0 CLK COMMAND BANK n
Read - AP BANK n
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
WRITE - AP BANK m
NOP
NOP
NOP Idle tRP - BANK m Write-Back
READ with Burst of 4 Page Active Page Active
BANK n, COL a BANK m, COL b
Interrupt Burst, Precharge tRP - BANK n WRITE with Burst of 4
Internal States
BANK m ADDRESS DQM DQ
DOUT a CAS Latency - 3 (BANK n)
DIN b
DIN b+1
DIN b+2
DIN b+3 DON'T CARE
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
31
IS42S32200E, IS45S32200E
WRITE with Auto Precharge
3.InterruptedbyaREAD(withorwithoutautoprecharge): AREADtobankmwillinterruptaWRITEonbankn when registered, with the data-out appearing CAS latency later.ThePRECHARGEtobanknwillbeginaftertwr is met, where twrbeginswhentheREADtobankmis registered.ThelastvalidWRITE to bank n will be data-in registeredoneclockpriortotheREADtobankm. 4.InterruptedbyaWRITE(withorwithoutautoprecharge): AWRITE to bank m will interrupt a WRITE on bank n when registered.ThePRECHARGEtobanknwillbeginafter twr is met, where twrbeginswhentheWRITEtobank misregistered.ThelastvaliddataWRITEtobankn willbedataregisteredoneclockpriortoaWRITEto bank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
T0 CLK T1 T2 T3 T4 T5 T6 T7
COMMAND
NOP
WRITE - AP BANK n
NOP
READ - AP BANK m
NOP
NOP
NOP
NOP
BANK n
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n tRP - BANK m Precharge
Internal States
BANK m Page Active
BANK n, COL a BANK m, COL b
READ with Burst of 4
ADDRESS
DQ
DIN a
DIN a+1 CAS Latency - 3 (BANK m)
DOUT b
DOUT b+1 DON'T CARE
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
T0 CLK T1 T2 T3 T4 T5 T6 T7
COMMAND
NOP
WRITE - AP BANK n
NOP
NOP
WRITE - AP BANK m
NOP
NOP
NOP
BANK n
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n tRP - BANK m Write-Back
Internal States
BANK m Page Active
BANK n, COL a BANK m, COL b
WRITE with Burst of 4
ADDRESS
DQ
DIN a
DIN a+1
DIN a+2
DIN b
DIN b+1
DIN b+2
DIN b+3 DON'T CARE
32
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Vdd max Vddq max ViN Vout Pd max Ics Topr Tstg Parameters MaximumSupplyVoltage MaximumSupplyVoltageforOutputBuffer InputVoltage OutputVoltage AllowablePowerDissipation outputShortedCurrent operatingTemperature Com. Ind. A1: A2: StorageTemperature Rating -1.0to+4.6 -1.0to+4.6 -1.0to+4.6 -1.0to+4.6 1 50 0 to +70 -40to+85 -40to+85 -40to+105 -55to+150 Unit V V V V W mA C
C
DC RECOMMENDED OPERATING CONDITIONS(2,5)
(Ta=0Cto+70CforCom.grade.Ta=-40Cto+85CforInd.andA1grade,Ta=-40Cto+105CforA2grade)

Symbol Vdd, Vddq Vih Vil
Parameter SupplyVoltage InputHighVoltage(3) InputLowVoltage(4)
Min. 3.0 2.0 -0.3
Typ. 3.3 -- --
Max. 3.6 Vdd +0.3 +0.8
Unit V V V
CAPACITANCE CHARACTERISTICS(1,2) (AtTa=0to+25C,Vdd=Vddq=3.30.3V,f=1MHz)
Symbol CiN1 CiN2 CI/O Parameter InputCapacitance:A0-A10,BA0,BA1 InputCapacitance:(CLK,CKE, CS, RAS, CAS, WE,LDQM,UDQM) DataInput/OutputCapacitance:DQ0-DQ31 Typ. -- -- -- Max. 4 4 5 Unit pF pF pF
Notes: 1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.Thisisa stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffect reliability. 2. AllvoltagesarereferencedtoGND. 3. Vih(max)=Vddq+1.2Vwithapulsewidth3ns.Theplusewidthcannotbegreaterthanonethirdofthecyclerate. 4. Vil(min)=GND-1.2Vwithapulse<3ns.Theplusewidthcannotbegreaterthanonethirdofthecyclerate. 5.Aninitialpauseof100usisrequiredafterpowerup,followedbytwoAUTOREFRESHcommands,beforeproperdeviceoperationisensured.(VddandVddQmustbepoweredupsimultaneously.GNDandGNDQmustbeatsamepotential.)Thetwo AUTOREFRESHcommandwake-upsshouldberepeatedanytimethetrefrefreshrequirementisexceeded.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
33
IS42S32200E, IS45S32200E
DC ELECTRICAL CHARACTERISTICS 1 (RecommendedOperationConditionsunlessotherwisenoted.)
Symbol idd1 (1) idd2p idd2ps idd2N (2) Idd2Ns idd3N (2) Idd3Ns Idd3p Idd3ps idd4 idd5 idd6 Parameter OperatingCurrent PrechargeStandbyCurrent (InPower-DownMode) PrechargeStandbyCurrent (InPower-DownMode) PrechargeStandbyCurrent (InNonPower-DownMode) PrechargeStandbyCurrent (InNonPower-DownMode) Active Standby Current (InNonPower-DownMode) Active Standby Current (InNonPower-DownMode) ActiveStandbyCurrent (Power-DownMode) ActiveStandbyCurrent (Power-DownMode) OperatingCurrent Auto-RefreshCurrent Self-RefreshCurrent Test Condition Onebankactive,CL=3,BL=1, tclk=tclk(min),trc=trc(min) CKE Vil (max),tck=15ns CKE Vil (max),CLK Vil (max) CS Vdd-0.2V,CKE Vih (miN) tck=15ns CS Vdd-0.2V,CKE Vih (miN)or CKE Vil (max),Allinputsstable CS Vdd-0.2V,CKE Vih (miN) tck=15ns CS Vdd-0.2V,CKE Vih (miN)or CKE Vil (max),Allinputsstable CKE Vil (max),tck=15ns CKE Vil (max),CLK Vil (max) Allbanksactive,BL=4,CL=3, tck=tck(min) trc=trc(min),tclk=tclk(min) CKE 0.2V -5 180 2 2 45 30 55 30 8 8 200 150 2 -6 150 2 2 45 30 55 30 8 8 160 130 2 -7 130 2 2 45 30 55 30 8 8 140 120 2 -75E 130 2 2 45 30 55 30 8 8 160 130 2 Unit mA mA mA mA mA mA mA mA mA mA mA mA
Notes: 1. Idd (max)isspecifiedattheoutputopencondition. 2. Input signals are changed one time during 30ns. 3.Testconditionfor-75EisCL=2.
DC ELECTRICAL CHARACTERISTICS 2 (RecommendedOperationConditionsunlessotherwisenoted.)
Symbol iil iol Voh Vol Parameter InputLeakageCurrent OutputLeakageCurrent OutputHighVoltageLevel OutputLowVoltageLevel Test Condition 0VVinVdd,withpinsotherthan thetestedpinat0V Outputisdisabled,0VVoutVdd, Ioh=-2mA Iol=2mA Min -5 -5 2.4 -- Max 5 5 -- 0.4 Unit A A V V
34
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
AC ELECTRICAL CHARACTERISTICS (1,2,3)
Symbol tck3 tck2 tac3 tac2 tch tcl toh tlz thz3 thz2 tds tdh tas tah tcks tckh tcka tcs tch trc tras trp trcd trrd Parameter ClockCycleTime Condition CASLatency=3 CASLatency=2 AccessTimeFromCLK(4) CASLatency=3 CASLatency=2 CLKHIGHLevelWidth CLKLOWLevelWidth OutputDataHoldTime OutputLOWImpedanceTime OutputHIGHImpedanceTime(5) CASLatency=3 CASLatency=2 InputDataSetupTime InputDataHoldTime AddressSetupTime AddressHoldTime CKESetupTime CKEHoldTime CKEtoCLKRecoveryDelayTime CommandSetupTime(CS, RAS, CAS, WE,DQM) CommandHoldTime(CS, RAS, CAS, WE,DQM) CommandPeriod(REFtoREF/ACTtoACT) CommandPeriod(ACTtoPRE) CommandPeriod(PREtoACT) ActiveCommandToRead/WriteCommandDelayTime CommandPeriod(ACT[0]toACT[1]) -5 Min. Max. 5 -- 10 -- -- 5 -- 8 2 -- 2 -- 2.5 -- 0 -- -- 5 -- 8 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1CLK+3 -- 1.5 -- 0.8 -- 55 -- 40 120K 15 -- 15 -- 10 -- -6 Min. Max. 6 -- 10 -- -- 5.5 -- 8 2.5 -- 2.5 -- 2.5 -- 0 -- -- 5.5 -- 8 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1CLK+3 -- 1.5 -- 0.8 -- 60 -- 42 120K 18 -- 18 -- 12 -- -7 Min. Max. 7 -- 10 -- -- 5.5 -- 8 2.5 -- 2.5 -- 2.5 -- 0 -- -- 5.5 -- 8 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1.5 -- 0.8 -- 1CLK+3 -- 1.5 -- 0.8 -- 70 -- 42 120K 20 -- 20 -- 14 -- -75E Min. Max. Units -- -- ns 7.5 -- ns -- -- ns -- 5.5 ns 2.5 -- ns 2.5 -- ns 2.5 -- ns 0 -- ns -- -- ns -- 5.5 ns 1.5 -- ns 0.8 -- ns 1.5 -- ns 0.8 -- ns 1.5 -- ns 0.8 -- ns 1CLK+3 -- ns 1.5 -- ns 0.8 -- ns 67.5 -- ns 45 120K ns 15 -- ns 15 -- ns 15 -- ns
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
35
IS42S32200E, IS45S32200E
AC ELECTRICAL CHARACTERISTICS (1,2,3)
Symbol tdpl3 tdpl2 tdal3 tdal2 tt twr txsr tref Parameter InputDataToPrecharge CommandDelaytime Condition CASLatency=3 -5 Min. Max. 2CLK -- -- -- -6 Min. Max. 2CLK -- 2CLK -- 2CLK+trp -- -7 Min. Max. 2CLK -- 2CLK -- 2CLK+trp -- 2CLK+trp 0.3 1CLK+7ns 77 -- -75E Min. Max. Units -- -- ns 2CLK -- -- -- ns ns ns ns tck ns ms ms ms
CAS Latency=2 2CLK InputDataToActive/Refresh CASLatency=3 2CLK+trp CommandDelaytime(DuringAuto-Precharge) CAS Latency=2 2CLK+trp TransitionTime(2) 0.3 WriteRecoveryTime 1CLK+5ns ExitSelfRefreshandActiveCommand(6) 60 o RefreshCycleTime(4096) Ta 70 C Com,Ind, -- A1, A2 Ta 85oC Ind,A1,A2 -- Ta>85oC A2 --
-- 2CLK+trp -- 1.2 0.3 1.2 -- 1CLK+6ns -- -- 66 -- 64 -- 64 -- -- -- 64 -- --
-- 2CLK+trp -- 1.2 0.3 1.2 -- 1CLK+7.5ns -- -- 75 -- 64 -- 64 -- 64 -- --
-- 64 -- 16
Notes: 1. Aninitialpauseof100usisrequiredafterpowerup,followedbytwoAUTOREFRESHcommands,beforeproperdeviceoperationisensured.(VddandVddqmustbepoweredupsimultaneously.GNDandGNDQmustbeatsamepotential.)Thetwo AUTOREFRESHcommandwake-upsshouldberepeatedanytimethetrefrefreshrequirementisexceeded. 2. measured with tt =0.5ns. 3. Thereferencelevelis1.5Vwhenmeasuringinputsignaltiming.Rise/falltimesaremeasuredbetweenVih (min.)andVil (max.). 4. Accesstimeismeasuredat1.5Vwiththeloadshowninthefigurebelow. 5. Thetimethz (max.)isdefinedasthetimerequiredfortheoutputvoltagetotransitionby200mVfromVoh (min.)orVol(max.) when the output is in the high impedance state. 6.CLKmustbetoggledaminimumoftwotimesduringthisperiod.
36
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
OPERATING FREQUENCY / LATENCY RELATIONSHIPS(1)
SYMBOL -- -- tccd tcked tped tdqd tdqm tdqz tdwd tdal tdpl tbdl tcdl trdl tmrd troh PARAMETER CONDITION ClockCycleTime OperatingFrequency CL=3 READ/WRITEcommandtoREAD/WRITEcommand CKEtoclockdisableorpower-downentrymode CKEtoclockenableorpower-downexitsetupmode DQMtoinputdatadelay DQMtodatamaskduringWRITEs DQMtodatahigh-impedanceduringREADs WRITEcommandtoinputdatadelay Data-intoACTIVEcommand CL=3 CL=2 Data-intoPRECHARGEcommand Lastdata-intoburstSTOPcommand Lastdata-intonewREAD/WRITEcommand Lastdata-intoPRECHARGEcommand LOADMODEREGISTERcommand toACTIVEorREFRESHcommand Data-outtohigh-impedancefrom CL=3 PRECHARGEcommand CL=2 -5 5 2001 1 1 1 0 0 2 0 5 4 2 1 1 2 2 3 2 -6 6 1661 1 1 1 0 0 2 0 5 4 2 1 1 2 2 3 2 -7 7 1431 1 1 1 0 0 2 0 5 4 2 1 1 2 2 3 2 -75E 7.5 1332 1 1 1 0 0 2 0 -- 4 2 1 1 2 2 -- 2 UNITS ns MHz cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
Note: 1.IfCL=2,theminimumtck2is10nsfor-5,-6and-7. 2.For-75E.CASLatency=2.
AC TEST CONDITIONS (Input/OutputReferenceLevel:1.4V) Input Load
tCK tCHI
3V
Output Load
tCL
CLK 1.4V
0V 3V
50
tCS tCH
I/O 30 pF
+1.4V
INPUT 1.4V
0V
tOH OUTPUT
1.4V
tAC
1.4V
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
37
IS42S32200E, IS45S32200E
INITIALIzE AND LOAD MODE REGISTER
T0 CLK
tCK
T1
Tn+1 tCH
To+1 tCL
Tp+1
Tp+2
Tp+3
tCKS tCKH CKE tCMH tCMS COMMAND DQM0-DQM3 A0-A9 A10 BA0, BA1 DQ T Power-up: VCC and CLK stable T = 100s Min. tRP Precharge all banks tRFC AUTO REFRESH tRFC AUTO REFRESH tMRD Program MODE REGISTER DON'T CARE ALL BANKS SINGLE BANK ALL BANKS BANK tAS tAH CODE tAS tAH CODE ROW ROW NOP tCMH tCMS PRECHARGE tCMH tCMS
AUTO REFRESH
NOP
AUTO REFRESH
NOP
Load MODE REGISTER
NOP
ACTIVE
38
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
POWER-DOWN MODE CYCLE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 A10 ALL BANKS ROW SINGLE BANK tAS tAH BANK High-Z Two clock cycles Precharge all active banks All banks idle, enter power-down mode Input buffers gated off while in power-down mode All banks idle BANK PRECHARGE NOP NOP NOP ACTIVE tCK T1 tCL tCKS T2 tCH tCKS Tn+1 Tn+2
ROW
BA0, BA1 DQ
Exit power-down mode
DON'T CARE
CASlatency=2,3
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
39
IS42S32200E, IS45S32200E
CLOCK SUSPEND MODE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 A10 BA0, BA1 tAS tAH COLUMN m(2) tAS tAH tAS tAH BANK tAC DOUT m tLZ tOH DON'T CARE UNDEFINED tAC tHZ DOUT m+1 BANK tDS tDH DIN N DIN N +1 COLUMN n READ NOP tCMS tCMH NOP NOP NOP NOP WRITE NOP T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK
tCL
tCH
tCKS tCKH
DQ
CASlatency=2,burstlength=2
40
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
AUTO-REFRESH CYCLE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 A10 BA0, BA1 DQ ALL BANKS ROW SINGLE BANK BANK(s) tAS tAH High-Z tRP tRFC tRFC DON'T CARE
CASlatency=2,3
Auto Refresh Auto Refresh
tCK
T1
tCL
T2
tCH
Tn+1
To+1
PRECHARGE
NOP
NOP
NOP
ACTIVE
ROW
BANK
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
41
IS42S32200E, IS45S32200E
SELF-REFRESH CYCLE
T0 CLK tCK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 A10 ALL BANKS SINGLE BANK tAS tAH BANK High-Z tRP Precharge all active banks Enter self refresh mode tXSR CLK stable prior to exiting Exit self refresh mode self refresh mode (Restart refresh time base) DON'T CARE PRECHARGE NOP
Auto Refresh
T1 tCH tCL
T2 tCKS
Tn+1
To+1
To+2
tRAS tCKS NOP NOP
Auto Refresh
BA0, BA1 DQ
Note: 1.Self-RefreshModeisnotsupportedforA2gradewithTa>85oC.
42
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
READ WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS A0-A9 A10 BA0, BA1 DQ tRCD tRAS tRC tAH COLUMN m ALL BANKS ROW DISABLE AUTO PRECHARGE BANK tAC tLZ CAS Latency tAC DOUT m tOH tAC DOUT m+1 tOH SINGLE BANK BANK tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH DON'T CARE UNDEFINED BANK ROW ACTIVE NOP READ tCMS tCMH NOP NOP NOP PRECHARGE NOP ACTIVE T1 T2 T3 T4 T5 T6 T7 T8
tCK
tCL
tCH
ROW tAS tAH ROW tAS tAH BANK
CAS latency = 2, Burst Length = 4
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
43
IS42S32200E, IS45S32200E
READ WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS A0-A9 A10 BA0, BA1 DQ tRCD tRAS tRC tAH COLUMN m) ENABLE AUTO PRECHARGE ROW BANK tAC tLZ CAS Latency tAC DOUT m tOH tAC DOUT m+1 tOH tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH DON'T CARE UNDEFINED BANK ROW ACTIVE NOP READ tCMS tCMH NOP NOP NOP NOP NOP ACTIVE T1 T2 T3 T4 T5 T6 T7 T8
tCK
tCL
tCH
ROW tAS tAH ROW tAS tAH BANK
CAS latency = 2, Burst Length = 4
44
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
SINGLE READ WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS A0-A9 A10 BA0, BA1 DQ tRCD tRAS tRC tAH COLUMN m ALL BANKS ROW DISABLE AUTO PRECHARGE BANK tAC tLZ CAS Latency tOH DOUT m tHZ tRP DON'T CARE UNDEFINED SINGLE BANK BANK BANK ROW ACTIVE NOP READ tCMS tCMH NOP NOP PRECHARGE NOP ACTIVE NOP T1 T2 T3 T4 T5 T6 T7 T8
tCK
tCL
tCH
ROW tAS tAH ROW tAS tAH BANK
CAS latency = 2, Burst Length = 1
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
45
IS42S32200E, IS45S32200E
SINGLE READ WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS A0-A9, A10 BA0, BA1 DQ tRCD tRAS tRC tAH COLUMN m ENABLE AUTO PRECHARGE ROW BANK tAC tOH DOUT m CAS Latency tRP tHZ DON'T CARE UNDEFINED BANK ROW
ACTIVE NOP NOP NOP READ NOP NOP ACTIVE NOP
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
tCMS tCMH
ROW tAS tAH ROW tAS tAH BANK
CAS latency = 2, Burst Length = 1
46
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
ALTERNATING BANK READ ACCESSES
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 BANK 0 tLZ tAC tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 DON'T CARE CAS Latency - BANK 0 tRCD - BANK 3 COLUMN m ENABLE AUTO PRECHARGE ROW BANK 3 tOH DOUT m tAC tOH DOUT m+1 tAC BANK 3 tOH DOUT m+2 tAC tRP - BANK 0 CAS Latency - BANK 3 tOH DOUT m+3 tAC ROW COLUMN b(2) ENABLE AUTO PRECHARGE ROW BANK 0 tOH DOUT b tAC tRCD - BANK 0 ROW ACTIVE NOP READ tCMS tCMH NOP ACTIVE NOP READ NOP ACTIVE T1 T2 T3 T4 T5 T6 T7 T8
tCK
tCL
tCH
DQ
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
47
IS42S32200E, IS45S32200E
READ - FULL-PAGE BURST
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9, A10 BA0, BA1 DQ tAS tAH
ACTIVE
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
NOP
READ
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
tCMS tCMH
ROW tAS tAH ROW tAS tAH BANK
COLUMN m
BANK tAC tLZ tRCD CAS Latency DOUT m tOH tAC tAC DOUT m+1 tOH each row (x32) has 256 locations tAC DOUT m+2 tOH tAC DOUT m-1 tOH tAC DOUT m tOH tHZ DOUT m+1 tOH DON'T CARE Full-page burst not self-terminating. Use BURST TERMINATE command. UNDEFINED
Full page completion
48
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
READ - DQM OPERATION
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS A0-A9 A10 BA0, BA1 DQ tAH ACTIVE
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
NOP
READ tCMS tCMH
NOP
NOP
NOP
NOP
NOP
NOP
ROW tAS tAH ROW tAS tAH BANK
COLUMN m
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK tAC tLZ tRCD CAS Latency tOH DOUT m tHZ tLZ tAC tOH DOUT m+2 tAC tOH DOUT m+3 tHZ DON'T CARE UNDEFINED
CAS Latency = 2, Burst Length = 4
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
49
IS42S32200E, IS45S32200E
WRITE - WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK COLUMN m ALL BANKS ROW DISABLE AUTO PRECHARGE BANK tDS DQ tRCD tRAS tRC tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH SINGLE BANK BANK BANK ROW ACTIVE NOP WRITE tCMS tCMH NOP NOP NOP PRECHARGE NOP ACTIVE T1 T2 T3 T4 T5 T6 T7 T8
tCK
tCL
tCH
DIN m
DIN m+3 tWR tRP
DON'T CARE
Burst Length = 4
50
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
WRITE - WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 A10 BA0, BA1 DQ tRCD tRAS tRC tAS tAH ROW tAS tAH ROW tAS tAH BANK BANK tDS tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH COLUMN m ENABLE AUTO PRECHARGE ROW BANK ROW ACTIVE NOP WRITE tCMS tCMH NOP NOP NOP NOP NOP NOP ACTIVE T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK
tCL
tCH
DIN m
DIN m+3 tWR tRP
DON'T CARE
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
51
IS42S32200E, IS45S32200E
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
NOP
WRITE tCMS tCMH
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
COLUMN m
ROW
ALL BANKS
ROW
DISABLE AUTO PRECHARGE SINGLE BANK
BANK tDS tDH
BANK
BANK
DQ tRCD tRAS tRC
DIN m tWR tRP DON'T CARE
52
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
SINGLE WRITE - WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 A10 BA0, BA1 tAS tAH ACTIVE
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
WRITE tCMS tCMH
NOP
NOP
NOP
ACTIVE
NOP
ROW tAS tAH ROW tAS tAH BANK
COLUMN m ENABLE AUTO PRECHARGE
ROW ROW
BANK tDS tDH
BANK
DQ tRCD tRAS tRC
DIN m tWR tRP DON'T CARE
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
53
IS42S32200E, IS45S32200E
ALTERNATING BANK WRITE ACCESS
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 BANK 0 tDS DQ tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 tDH tDS tDH DIN m+1 COLUMN m ENABLE AUTO PRECHARGE ROW BANK 1 tDS tDH DIN m+2 tDS tDH BANK 1 tDS tDH DIN b tDS tDH tDS tDH ROW COLUMN b ENABLE AUTO PRECHARGE ROW BANK 0 tDS tDH ROW ACTIVE NOP WRITE tCMS tCMH NOP ACTIVE NOP WRITE NOP NOP ACTIVE T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK
tCL
tCH
DIN m
DIN m+3
DIN b+1
DIN b+2
DIN b+3 tRCD - BANK 0 tWR - BANK 1
tWR - BANK 0 tRCD - BANK 1
tRP - BANK 0
DON'T CARE
54
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
WRITE - FULL PAGE BURST
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS A0-A9 A10 BA0, BA1 DQ tRCD tAH COLUMN m
ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP
T1 tCK tCL
T2 tCH
T3
T4
T5
Tn+1
Tn+2
tCMS tCMH
ROW tAS tAH ROW tAS tAH BANK
BANK tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH DIN m DIN m+1 DIN m+2 DIN m+3
256 locations within same row
DIN m-1
Full-page burst does not self-terminate. Can use BURST TERMINATE to stop.
Full page completed
DON'T CARE
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
55
IS42S32200E, IS45S32200E
WRITE - DQM OPERATION
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 DQ tRCD ROW tAS tAH ROW tAS tAH BANK COLUMN m
ENABLE AUTO PRECHARGE
T1 tCK tCL
T2 tCH
T3
T4
T5
T6
T7
ACTIVE
NOP
WRITE tCMS tCMH
NOP
NOP
NOP
NOP
NOP
DISABLE AUTO PRECHARGE
BANK tDS tDH tDS tDH DIN m+2 tDS tDH DIN m DIN m+3 DON'T CARE
56
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
IS42S32200E, IS45S32200E
ORDERING INFORMATION Commercial Range: 0C to +70C
Frequency 200MHz 166MHz 143MHz Speed (ns) 5 6 7 Order Part No. IS42S32200E-5TL IS42S32200E-5BL IS42S32200E-6TL IS42S32200E-6BL IS42S32200E-6B IS42S32200E-7TL IS42S32200E-7BL IS42S32200E-7B Package 400-milTSOPII,Lead-free 90-ballBGA,Lead-free 400-milTSOPII,Leadfree 90-ballBGA,Lead-free 90-ballBGA 400-milTSOPII,Leadfree 90-ballBGA,Lead-free 90-ballBGA
Industrial Range: -40C to +85C
Frequency 166MHz 143MHz Speed (ns) 6 7 Order Part No. IS42S32200E-6TLI IS42S32200E-6BLI IS42S32200E-6BI IS42S32200E-7TLI IS42S32200E-7BLI Package 400-milTSOPII,Leadfree 90-ballBGA,Lead-free 90-ballBGA 400-milTSOPII,Leadfree 90-ballBGA,Lead-free
ORDERING INFORMATION Automotive Range: -40C to +85C
Frequency 166MHz 143MHz 133MHz Speed (ns) 6 7 7.5 Order Part No. IS45S32200E-6TLA1 IS45S32200E-6BLA1 IS45S32200E-7TLA1 IS45S32200E-7BLA1 IS45S32200E-7BA1 IS45S32200E-75ETLA1 IS45S32200E-75EBLA1 Package 400-milTSOPII,Leadfree 90-ballBGA,Lead-free 400-milTSOPII,Leadfree 90-ballBGA,Lead-free 90-ballBGA 400-milTSOPII,Leadfree 90-ballBGA,Lead-free
Automotive Range: -40C to +105C
Frequency 143MHz Speed (ns) 7 Order Part No. IS45S32200E-7TLA2 IS45S32200E-7BLA2 Package 400-milTSOPII,Leadfree 90-ballBGA,Lead-free
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
57
IS42S32200E, IS45S32200E
NOTE :
1. Controlling dimension : mm 2. Dimension D and E1 do not include mold protrusion .
3. Dimension b does not include dambar protrusion/intrusion.
4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test.
Package Outline
09/26/2006
58
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. B 07/23/09
D1
NOTE :
1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207
0.80
0.45
Package Outline
08/14/2008
Integrated Silicon Solution, Inc. -- www.issi.com
IS42S32200E, IS45S32200E
Rev. B 07/23/09
59

▲Up To Search▲

Price & Availability of IS42S32200E-6TL

	To Download IS42S32200E-6TL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .